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signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: 719-528-2300 fax: 719-528-2370 web site: http://www.spt.com e-mail: sales@spt.com spt7725 8-bit, 300 msps, flash a/d converter technical data august 17, 2001 features ? metastable errors reduced to 1 lsb low input capacitance: 10 pf wide input bandwidth: 210 mhz 300 msps conversion rate typical power dissipation: 2.2 watts applications digital oscilloscopes transient capture radar, ew, ecm direct rf down-conversion medical electronics: ultrasound, cat instrumentation general description the spt7725 is a monolithic flash a/d converter capable of digitizing a two volt analog input signal into 8-bit digital words at a 300 msps (typ) update rate. for most applications, no external sample-and-hold is re- quired for accurate conversion due to the device?s narrow aperture time, wide bandwidth, and low input capacitance. a single standard ?5.2 volt power supply is required for operation of the spt7725, with nominal power dissipation of 2.2 w. a proprietary decoding scheme reduces meta- stable errors to the 1 lsb level. the spt7725 is available in 42-lead ceramic sidebrazed dip, surface-mount 44-lead cerquad, and 46-lead pga packages (all are pin-compatible with the spt7710); the cerquad and pga packages allow access to additional reference ladder taps, an overrange bit, and a data ready output. the spt7725 is available in the industrial tem- perature range.

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spt 2 8/17/01 spt7725 absolute maximum ratings (beyond which damage may occur) 1 25 c note: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied conditions in typical applications. supply voltages negative supply voltage (v ee to gnd) ?7.0 to +0.5 v ground voltage differential .................... ?0.5 to +0.5 v input voltage analog input voltage ............................... v ee to +0.5 v reference input voltage .......................... v ee to +0.5 v digital input voltage ................................ v ee to +0.5 v reference current v rtf to v rbf ........................ 25 ma output digital output current ............................... 0 to ?30 ma temperature operating temperature,ambient ............. ?25 to +85 c junction ...................... +150 c lead temperature, (soldering 10 seconds) ..... +300 c storage temperature ............................ ?65 to +150 c electrical specifications t a = t min to t max , v ee =?5.2 v, r source =50 ? , v rbf =?2.00 v, v r2 =?1.00 v, v rtf =0.00 v, ? clk =250 mhz, duty cycle=50%, unless otherwise specified. test test spt7725a spt7725b parameters conditions level min typ max min typ max units dc accuracy integral linearity error ? clk = 100 khz vi ?0.75 0.60 +0.75 ?0.95 0.80 +0.95 lsb differential linearity error ? clk = 100 khz vi ?0.75 +0.75 ?0.95 +0.95 lsb no missing codes guaranteed guaranteed analog input offset error v rt vi ?30 +30 ?30 +30 mv offset error v rb vi ?30 +30 ?30 +30 mv input voltage range vi ?2.0 0.0 ?2.0 0.0 volts input capacitance over full input range v 10 10 pf input resistance v 15 15 k ? input current vi 250 500 250 500 a input slew rate v 1,000 1,000 v/s large signal bandwidth v in =f.s. v 210 210 mhz small signal bandwidth v in =500 mv p-p v 335 335 mhz clock synchronous input currents v 40 40 a reference input ladder resistance vi 100 200 300 100 200 300 ? reference bandwidth v 10 10 mhz timing characteristics maximum sample rate iv 250 300 250 300 msps clock to data delay v 2.4 2.4 ns output delay tempco v 2 2 ps/c clk-to-data ready delay (t d ) v 2.0 2.0 ns aperture jitter v 5 5 ps acquisition time v 1.5 1.5 ns dynamic performance signal-to-noise ratio ? in = 3.58 mhz vi 45 47 44 46 db ? in = 50 mhz vi 39 42 38 41 db total harmonic distortion ? in = 3.58 mhz vi ?52 ?48 ?50 ?46 db ? in = 50 mhz vi ?43 ?40 ?42 ?39 db signal-to-noise and distortion ? in = 3.58 mhz vi 44 46 42 44 db (sinad) ? in = 50 mhz vi 37 39 35 37 db
spt 3 8/17/01 spt7725 test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- formed during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. unless otherwise noted, all test are pulsed tests; therefore, t j = t c = t a . level test procedure i 100% production tested at the specified temperature. ii 100% production tested at t a = +25 c, and sample tested at the specified temperatures. iii qa sample tested only at the specified temperatures. iv parameter is guaranteed (but not tested) by design and characteri- zation data. v parameter is a typical value for information purposes only. vi 100% production tested at t a = +25 c. parameter is guaranteed over specified temperature range. electrical specifications t a = t min to t max , v ee =?5.2 v, r source =50 ? , v rbf =?2.00 v, v r2 =?1.00 v, v rtf =0.00 v, ? clk =250 mhz, duty cycle=50%, unless otherwise specified. test test spt7725a spt7725b parameters conditions level min typ max min typ max units digital inputs digital input high voltage (minv, linv) vi ?1.1 ?0.7 ?1.1 ?0.7 volts digital input low voltage (minv, linv) vi ?2.0 ?1.5 ?2.0 ?1.5 volts clock low width, t pwl vi 2.2 2.0 2 1.8 ns clock high width, t pwh vi 2.2 2.0 2 1.8 ns digital outputs digital output high voltage 50 ? to ?2 v vi ?1.1 ?1.1 volts digital output low voltage 50 ? to ?2 v vi ?1.5 ?1.5 volts power supply requirements supply current +25 c vi 425 550 425 550 ma power dissipation +25 c vi 2.2 2.9 2.2 2.9 w
spt 4 8/17/01 spt7725 typical performance characteristics snr vs input frequency thd vs input frequency sinad vs input frequency snr, thd, sinad vs temperature / // / / "#
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* , general description the spt7725 is a fast monolithic 8-bit parallel flash a/d converter. the nominal conversion rate is 300 msps and the analog bandwidth is in excess of 200 mhz. a major ad- vance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators. (see block diagram.) this not only re- duces clock transient kickback to the input and reference ladder due to a low ac beta but also reduces the effect of the dynamic state of the input signal on the latching char- acteristics of the input comparators. the preamplifiers act as buffers and stabilize the input capacitance so that it re- mains constant for varying input voltages and frequencies and, therefore, makes the part easier to drive than previ- ous flash converters. the spt7725 incorporates a propri- etary decoding scheme that reduces metastable errors (sparkle codes or flyers ) to a maximum of 1 lsb. the spt7725 has true differential analog and digital data paths from the preamplifiers to the output buffers (current mode logic) for reducing potential missing codes while rejecting common mode noise. signature errors are also reduced by careful layout of the analog circuitry. every comparator also has a clock buffer to reduce differential delays and to improve signal-to- noise ratio. the output drive capability of the device can provide full ecl swings into 50 ? loads. typical interface circuit the typical interface circuit is shown in figure 1. the spt7725 is relatively easy to apply depending on the accuracy needed in the intended application. wire-wrap may be employed with careful point-to-point ground con- nections if desired, but to achieve the best operation, a
spt 6 8/17/01 spt7725 double-sided pc board with a ground plane on the compo- nent side separated into digital and analog sections will give the best performance. the converter is bonded-out to place the digital pins on the left side of the package and the analog pins on the right side. additionally, an rf bead connection through a single point from the analog to digi- tal ground planes will reduce ground noise pickup. the circuit in figure 2 (pga and cerquad packages only) is intended to show the most elaborate method of achieving the least error by correcting for integral nonlinearity, input induced distortion, and power supply/ground noise. this is achieved by the use of external reference ladder tap con- nections, an input buffer, and supply decoupling. the func- tion of each pin and external connections to other compo- nents is as follows: figure 2 ? typical interface circuit 2 (pga and cerquad packages only) ( ( / ( * ? < 5/ >&

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5/ >& 5/ >& 5 >& ? < @ / ( c 5/ >& 5 >& ( < ( ( *& ( ? < @ 5/ >& v ee , agnd, dgnd v ee is the supply pin with agnd as ground for the device. the power supply pins should be bypassed as close to the device as possible with at least a .01 f ceramic capaci- tor. a 1 f tantalum should also be used for low frequency suppression. dgnd is the ground for the ecl outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 1. v in (analog input) there are two analog input pins that are tied to the same point internally. either one may be used as an analog input sense and the other for input force . this is convenient for testing the source signal to see if there is sufficient drive capability. the pins can also be tied together and driven by
spt 7 8/17/01 spt7725 the same source. the spt7725 is superior to similar de- vices, due to a preamplifier stage before the comparators. this makes the device easier to drive because it has con- stant capacitance and induces less slew rate distortion. an optional input buffer may be used. clk, clk (clock inputs) the clock inputs are designed to be driven differentially with ecl levels. the clock may be driven single-ended since clk is internally biased to ? 1.3 v. (see clock input circuit.) clk may be left open, but a .01 f bypass capaci- tor from clk to agnd is recommended. note: system performance may be degraded due to increased clock noise or jitter. minv, linv (output logic control) these are ecl-compatible digital controls for changing the output code from straight binary to two ? s complement, etc. for more information, see table i. both minv and linv are in the logic low (0) state when they are left open. the high state can be obtained by tying to agnd through a diode or 3.9 k ? resistor. d0 to d7 (digital outputs) the digital outputs can drive ecl levels into 50 ? when pulled down to ? 2 v. when pulled down to ? 5.2 v, the out- puts can drive 150 ? to 1 k ? loads. v rbf , v r2 , v rtf (reference inputs) there are two reference inputs and one external reference voltage tap. these are ? 2 v (v rbf ), mid-tap (v r2 ), and agnd (v rtf ). the reference pins can be driven as shown in figure 1. v r2 should be bypassed to agnd for further noise suppression. v rbf , v rbs , v r1 , v r2 , v r3 , v rtf , v rts reference inputs (pga and cerquad packages only) these are five external reference voltage taps from ? 2 v (v rbf ) to agnd (v rtf ) that can be used to control integral linearity over temperature. the taps can be driven by op amps as shown in figure 2. these voltage level inputs can be bypassed to agnd for further noise suppression if so desired. v rb and v rt have force and sense pins for moni- toring the top and bottom voltage references. n/c all not connected pins should be tied to dgnd on the left side of the package and to agnd on the right side of the package. dread ? data ready; drinv ? data ready inverse (pga and cerquad packages only) the data ready pin is a flag that goes high or low at the output when data is valid or ready to be received. it is es- sentially a delay line that accounts for the time neces- sary for information to be clocked through the spt7725 ? s decoders and latches. this function is useful for interfac- ing with high-speed memory. using the data ready output to latch the output data ensures minimum set-up and hold times. drinv is a data ready inverse control pin. (see the timing diagram.) d8 ? overrange (pga and cerquad packages only) this is an overrange function. when the spt7725 is in an overrange condition, d8 goes high and all data outputs go high as well. this makes it possible to include the spt7725 into higher resolution systems. binary twos complement true inverted true inverted minv=linv=0 minv=linv=1 minv=1; linv=0 minv=0; linv=1 analog input voltage d8 d7_____d0 d7_____d0 d7_____d0 d7_____d0 ? 2 v + 1/2 lsb 0 00000000 11111111 10000000 01111111 00000001 11111110 10000001 01111110 ? 1.0 v 0 01111111 10000000 11111111 00000000 10000000 01111111 00000000 11111111 0 v ? 1/2 lsb 0 11111111 00000000 01111111 10000000 11111110 00000001 01111110 10000001 0 v 1 11111111 00000000 01111111 10000000 table i ? output coding
spt 8 8/17/01 spt7725 operation the spt7725 has 256 preamp/comparator pairs that are each supplied with the voltage from v rtf to v rbf divided equally by the resistive ladder as shown in the block dia- gram. this voltage is applied to the positive input of each preamplifier/comparator pair. an analog input voltage ap- plied at v in is connected to the negative inputs of each preamplifier/comparator pair. the comparators are then clocked through each comparator ? s individual clock buffer. when clk pin is in the low state, the master or input stage of the comparators compares the analog input voltage to the respective reference voltage. when clk changes from low to high, the comparators are latched to the state prior to the clock transition and output logic codes in sequence from the top comparators, closest to v rtf (0 v), down to the point where the magnitude of the input signal changes sign (thermometer code). the output of each comparator is then registered into four 64-to-6 bit decod- ers when clk is changed from high to low. at the output of the decoders is a set of four 7-bit latches that are enabled ( track ) when clk changes from high to low. from here, the outputs of the latches are coded into 6 lsbs from 4 columns, and 4 columns are coded into 2 msbs. next are the minv and linv controls for output inversions, which consist of a set of eight xor gates. finally, 8 ecl output latches and buffers are used to drive the external loads. the conversion takes one clock cycle from the input to the data outputs. figure 3 ? timing diagram
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* ( * & ( * * "( -"( * <5/ ( ( *,& * * ( " ( *& ( ) ) <5/ ( * * * * * * * * ( " / ) ) evaluation boards the eb7725 evaluation board is available to aid designers in demonstrating the full performance of the spt7725. this board includes a voltage reference circuit, clock driver circuit, output data latches, and an on-board recon- struction of the digital data. an application note describing the operation of this board, as well as application tips, is also available. contact the factory for price and delivery.
spt 10 8/17/01 spt7725 package outlines 42-lead sidebrazed dip " 7 h & 46-lead pin grid array 6
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1 inches millimeters symbol min max min max a 0.081 0.099 2.06 2.51 b 0.016 0.020 0.41 0.51 c 0.095 0.105 2.41 2.67 d .050 typ 1.27 e .050 typ 1.27 f 0.275 6.99 g 2.080 2.120 52.83 53.85 h 0.585 0.605 14.86 15.37 i 0.008 0.015 0.20 0.38 j 0.600 0.620 15.24 15.75 inches millimeters symbol min max min max a 0.890 0.910 22.61 23.11 b 0.100 typ 2.54 typ c .045 dia .055 dia 1.14 1.40 d 0.084 0.096 2.13 2.44 e 0.169 0.193 4.29 4.90 f .020 dia .030 dia 0.51 0.76 g .050 typ 1.27 typ
spt 11 8/17/01 spt7725 44-lead cerquad /<; & 7 inches millimeters symbol min max min max a 0.550 typ 13.97 typ b 0.685 0.709 17.40 18.00 c 0.037 0.041 0.94 1.04 d 0.016 typ 0.41 typ e 0.008 typ 0.20 typ f 0.027 0.051 0.69 1.30 g 0.006 typ 0.15 typ h 0.080 0.089 2.03 2.26
spt 12 8/17/01 spt7725 ordering information part number linearity temperature range package type spt7725aij 0.75 lsb ? 25 to +85 c 42l ceramic s/b spt7725bij 0.95 lsb ? 25 to +85 c 42l ceramic s/b spt7725aig 0.75 lsb ? 25 to +85 c 46l pga spt7725big 0.95 lsb ? 25 to +85 c 46l pga spt7725aiq 0.75 lsb ? 25 to +85 c 44l cerquad spt7725biq 0.95 lsb ? 25 to +85 c 44l cerquad spt7725bcu 0.95 lsb +25 c die* *please see the die specification for guaranteed electrical performance. signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited. warning ? life support applications policy ? spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty. pin assignments pin functions name function linv d0 through d6 output inversion control pin v ee negative analog supply nominally ? 5.2 v dgnd digital ground d0 digital data output (lsb) d1 ? d6 digital data output d7 digital data output (msb) minv d7 output inversion control pin clk inverse ecl clock input pin clk ecl clock input pin agnd analog ground v in analog input; can be connected to the input signal or used as a sense v r2 reference voltage tap 2 ( ? 1.0 v typ) v rtf reference voltage top v rbf reference voltage bottom ( " ( ( ( ( d / d / d / d / g "( / $% ' $-% ' ( -"( g ) ) g ( *,& g g g ( * g g ( g ( * & g ( " ( ( "( g *"( g ( ( *,% ( *,& / *i ( ( * ( " ( * ( " ( * ( ( -"( ) ) ( ( * % ( * & d / / d d / / d & 7 / g ( " ( * ( " g ( * & ( * % ( * ( ( * g ( ( *,& ( *,% ( ) ( ( g ( * -"( "( *"( ) d h the following pins are on pga and cerquad packages only. drinv data ready inverse dread data ready output overrange overrange output d8 v r1 reference voltage tap 1 ( ? 1.5 v typ) v r3 reference voltage tap 3 ( ? 0.5 v typ) v rts reference voltage top, sense v rbs reference voltage bottom, sense cerquad bottom view pga dip

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